837 lines
32 KiB
C++
837 lines
32 KiB
C++
/**
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* Marlin 3D Printer Firmware
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* Copyright (c) 2019 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* Software SPI functions originally from Arduino Sd2Card Library
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* Copyright (c) 2009 by William Greiman
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*
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* Completely rewritten and tuned by Eduardo José Tagle in 2017/2018
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* in ARM thumb2 inline assembler and tuned for maximum speed and performance
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* allowing SPI clocks of up to 12 Mhz to increase SD card read/write performance
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*/
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/**
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* Description: HAL for Arduino Due and compatible (SAM3X8E)
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*
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* For ARDUINO_ARCH_SAM
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*/
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#ifdef ARDUINO_ARCH_SAM
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// --------------------------------------------------------------------------
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// Includes
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// --------------------------------------------------------------------------
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#include "../../inc/MarlinConfig.h"
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#include "../shared/Delay.h"
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// --------------------------------------------------------------------------
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// Public Variables
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// --------------------------------------------------------------------------
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// --------------------------------------------------------------------------
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// Public functions
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// --------------------------------------------------------------------------
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#if EITHER(DUE_SOFTWARE_SPI, FORCE_SOFT_SPI)
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// --------------------------------------------------------------------------
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// software SPI
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// --------------------------------------------------------------------------
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// Make sure GCC optimizes this file.
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// Note that this line triggers a bug in GCC which is fixed by casting.
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// See the note below.
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#pragma GCC optimize (3)
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typedef uint8_t (*pfnSpiTransfer)(uint8_t b);
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typedef void (*pfnSpiRxBlock)(uint8_t* buf, uint32_t nbyte);
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typedef void (*pfnSpiTxBlock)(const uint8_t* buf, uint32_t nbyte);
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/* ---------------- Macros to be able to access definitions from asm */
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#define _PORT(IO) DIO ## IO ## _WPORT
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#define _PIN_MASK(IO) MASK(DIO ## IO ## _PIN)
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#define _PIN_SHIFT(IO) DIO ## IO ## _PIN
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#define PORT(IO) _PORT(IO)
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#define PIN_MASK(IO) _PIN_MASK(IO)
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#define PIN_SHIFT(IO) _PIN_SHIFT(IO)
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// run at ~8 .. ~10Mhz - Tx version (Rx data discarded)
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static uint8_t spiTransferTx0(uint8_t bout) { // using Mode 0
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uint32_t MOSI_PORT_PLUS30 = ((uint32_t) PORT(MOSI_PIN)) + 0x30; /* SODR of port */
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uint32_t MOSI_MASK = PIN_MASK(MOSI_PIN);
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uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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uint32_t idx = 0;
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/* Negate bout, as the assembler requires a negated value */
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bout = ~bout;
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/* The software SPI routine */
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__asm__ __volatile__(
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A(".syntax unified") // is to prevent CM0,CM1 non-unified syntax
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/* Bit 7 */
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A("ubfx %[idx],%[txval],#7,#1") /* Place bit 7 in bit 0 of idx*/
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#6,#1") /* Place bit 6 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 6 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#5,#1") /* Place bit 5 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 5 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#4,#1") /* Place bit 4 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 4 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#3,#1") /* Place bit 3 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 3 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#2,#1") /* Place bit 2 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 2 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#1,#1") /* Place bit 1 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 1 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[idx],%[txval],#0,#1") /* Place bit 0 in bit 0 of idx*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 0 */
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A("str %[mosi_mask],[%[mosi_port], %[idx],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("nop") /* Result will be 0 */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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: [idx]"+r"( idx )
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: [txval]"r"( bout ) ,
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[mosi_mask]"r"( MOSI_MASK ),
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[mosi_port]"r"( MOSI_PORT_PLUS30 ),
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[sck_mask]"r"( SCK_MASK ),
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[sck_port]"r"( SCK_PORT_PLUS30 )
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: "cc"
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);
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return 0;
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}
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// Calculates the bit band alias address and returns a pointer address to word.
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// addr: The byte address of bitbanding bit.
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// bit: The bit position of bitbanding bit.
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#define BITBAND_ADDRESS(addr, bit) \
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(((uint32_t)(addr) & 0xF0000000) + 0x02000000 + ((uint32_t)(addr)&0xFFFFF)*32 + (bit)*4)
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// run at ~8 .. ~10Mhz - Rx version (Tx line not altered)
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static uint8_t spiTransferRx0(uint8_t bout) { // using Mode 0
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uint32_t bin = 0;
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uint32_t work = 0;
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uint32_t BITBAND_MISO_PORT = BITBAND_ADDRESS( ((uint32_t)PORT(MISO_PIN))+0x3C, PIN_SHIFT(MISO_PIN)); /* PDSR of port in bitband area */
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uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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UNUSED(bout);
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/* The software SPI routine */
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__asm__ __volatile__(
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A(".syntax unified") // is to prevent CM0,CM1 non-unified syntax
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/* bit 7 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#7,#1") /* Store read bit as the bit 7 */
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/* bit 6 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#6,#1") /* Store read bit as the bit 6 */
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/* bit 5 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#5,#1") /* Store read bit as the bit 5 */
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/* bit 4 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#4,#1") /* Store read bit as the bit 4 */
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/* bit 3 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#3,#1") /* Store read bit as the bit 3 */
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/* bit 2 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#2,#1") /* Store read bit as the bit 2 */
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/* bit 1 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#1,#1") /* Store read bit as the bit 1 */
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/* bit 0 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bfi %[bin],%[work],#0,#1") /* Store read bit as the bit 0 */
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: [bin]"+r"(bin),
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[work]"+r"(work)
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: [bitband_miso_port]"r"( BITBAND_MISO_PORT ),
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[sck_mask]"r"( SCK_MASK ),
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[sck_port]"r"( SCK_PORT_PLUS30 )
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: "cc"
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);
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return bin;
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}
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// run at ~4Mhz
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static uint8_t spiTransfer1(uint8_t b) { // using Mode 0
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int bits = 8;
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do {
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WRITE(MOSI_PIN, b & 0x80);
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b <<= 1; // little setup time
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WRITE(SCK_PIN, HIGH);
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DELAY_NS(125); // 10 cycles @ 84mhz
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b |= (READ(MISO_PIN) != 0);
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WRITE(SCK_PIN, LOW);
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DELAY_NS(125); // 10 cycles @ 84mhz
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} while (--bits);
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return b;
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}
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// all the others
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static uint32_t spiDelayCyclesX4 = (F_CPU) / 1000000; // 4uS => 125khz
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static uint8_t spiTransferX(uint8_t b) { // using Mode 0
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int bits = 8;
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do {
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WRITE(MOSI_PIN, b & 0x80);
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b <<= 1; // little setup time
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WRITE(SCK_PIN, HIGH);
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__delay_4cycles(spiDelayCyclesX4);
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b |= (READ(MISO_PIN) != 0);
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WRITE(SCK_PIN, LOW);
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__delay_4cycles(spiDelayCyclesX4);
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} while (--bits);
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return b;
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}
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// Pointers to generic functions for byte transfers
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/**
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* Note: The cast is unnecessary, but without it, this file triggers a GCC 4.8.3-2014 bug.
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* Later GCC versions do not have this problem, but at this time (May 2018) Arduino still
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* uses that buggy and obsolete GCC version!!
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*/
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static pfnSpiTransfer spiTransferRx = (pfnSpiTransfer)spiTransferX;
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static pfnSpiTransfer spiTransferTx = (pfnSpiTransfer)spiTransferX;
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// Block transfers run at ~8 .. ~10Mhz - Tx version (Rx data discarded)
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static void spiTxBlock0(const uint8_t* ptr, uint32_t todo) {
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uint32_t MOSI_PORT_PLUS30 = ((uint32_t) PORT(MOSI_PIN)) + 0x30; /* SODR of port */
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uint32_t MOSI_MASK = PIN_MASK(MOSI_PIN);
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uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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uint32_t work = 0;
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uint32_t txval = 0;
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/* The software SPI routine */
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__asm__ __volatile__(
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A(".syntax unified") // is to prevent CM0,CM1 non-unified syntax
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L("loop%=")
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A("ldrb.w %[txval], [%[ptr]], #1") /* Load value to send, increment buffer */
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A("mvn %[txval],%[txval]") /* Negate value */
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/* Bit 7 */
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A("ubfx %[work],%[txval],#7,#1") /* Place bit 7 in bit 0 of work*/
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#6,#1") /* Place bit 6 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 6 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#5,#1") /* Place bit 5 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 5 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#4,#1") /* Place bit 4 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 4 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#3,#1") /* Place bit 3 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 3 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#2,#1") /* Place bit 2 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 2 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#1,#1") /* Place bit 1 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 1 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("ubfx %[work],%[txval],#0,#1") /* Place bit 0 in bit 0 of work*/
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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/* Bit 0 */
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A("str %[mosi_mask],[%[mosi_port], %[work],LSL #2]") /* Access the proper SODR or CODR registers based on that bit */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
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A("subs %[todo],#1") /* Decrement count of pending words to send, update status */
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A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
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A("bne.n loop%=") /* Repeat until done */
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: [ptr]"+r" ( ptr ) ,
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[todo]"+r" ( todo ) ,
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[work]"+r"( work ) ,
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[txval]"+r"( txval )
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: [mosi_mask]"r"( MOSI_MASK ),
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[mosi_port]"r"( MOSI_PORT_PLUS30 ),
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[sck_mask]"r"( SCK_MASK ),
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[sck_port]"r"( SCK_PORT_PLUS30 )
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: "cc"
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);
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}
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static void spiRxBlock0(uint8_t* ptr, uint32_t todo) {
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uint32_t bin = 0;
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uint32_t work = 0;
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uint32_t BITBAND_MISO_PORT = BITBAND_ADDRESS( ((uint32_t)PORT(MISO_PIN))+0x3C, PIN_SHIFT(MISO_PIN)); /* PDSR of port in bitband area */
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uint32_t SCK_PORT_PLUS30 = ((uint32_t) PORT(SCK_PIN)) + 0x30; /* SODR of port */
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uint32_t SCK_MASK = PIN_MASK(SCK_PIN);
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/* The software SPI routine */
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__asm__ __volatile__(
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A(".syntax unified") // is to prevent CM0,CM1 non-unified syntax
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L("loop%=")
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/* bit 7 */
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A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#7,#1") /* Store read bit as the bit 7 */
|
|
|
|
/* bit 6 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#6,#1") /* Store read bit as the bit 6 */
|
|
|
|
/* bit 5 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#5,#1") /* Store read bit as the bit 5 */
|
|
|
|
/* bit 4 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#4,#1") /* Store read bit as the bit 4 */
|
|
|
|
/* bit 3 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#3,#1") /* Store read bit as the bit 3 */
|
|
|
|
/* bit 2 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#2,#1") /* Store read bit as the bit 2 */
|
|
|
|
/* bit 1 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#1,#1") /* Store read bit as the bit 1 */
|
|
|
|
/* bit 0 */
|
|
A("str %[sck_mask],[%[sck_port]]") /* SODR */
|
|
A("ldr %[work],[%[bitband_miso_port]]") /* PDSR on bitband area for required bit: work will be 1 or 0 based on port */
|
|
A("str %[sck_mask],[%[sck_port],#0x4]") /* CODR */
|
|
A("bfi %[bin],%[work],#0,#1") /* Store read bit as the bit 0 */
|
|
|
|
A("subs %[todo],#1") /* Decrement count of pending words to send, update status */
|
|
A("strb.w %[bin], [%[ptr]], #1") /* Store read value into buffer, increment buffer pointer */
|
|
A("bne.n loop%=") /* Repeat until done */
|
|
|
|
: [ptr]"+r"(ptr),
|
|
[todo]"+r"(todo),
|
|
[bin]"+r"(bin),
|
|
[work]"+r"(work)
|
|
: [bitband_miso_port]"r"( BITBAND_MISO_PORT ),
|
|
[sck_mask]"r"( SCK_MASK ),
|
|
[sck_port]"r"( SCK_PORT_PLUS30 )
|
|
: "cc"
|
|
);
|
|
}
|
|
|
|
static void spiTxBlockX(const uint8_t* buf, uint32_t todo) {
|
|
do {
|
|
(void) spiTransferTx(*buf++);
|
|
} while (--todo);
|
|
}
|
|
|
|
static void spiRxBlockX(uint8_t* buf, uint32_t todo) {
|
|
do {
|
|
*buf++ = spiTransferRx(0xFF);
|
|
} while (--todo);
|
|
}
|
|
|
|
// Pointers to generic functions for block tranfers
|
|
static pfnSpiTxBlock spiTxBlock = (pfnSpiTxBlock)spiTxBlockX;
|
|
static pfnSpiRxBlock spiRxBlock = (pfnSpiRxBlock)spiRxBlockX;
|
|
|
|
#if MB(ALLIGATOR)
|
|
#define _SS_WRITE(S) WRITE(SS_PIN, S)
|
|
#else
|
|
#define _SS_WRITE(S) NOOP
|
|
#endif
|
|
|
|
void spiBegin() {
|
|
SET_OUTPUT(SS_PIN);
|
|
_SS_WRITE(HIGH);
|
|
SET_OUTPUT(SCK_PIN);
|
|
SET_INPUT(MISO_PIN);
|
|
SET_OUTPUT(MOSI_PIN);
|
|
}
|
|
|
|
uint8_t spiRec() {
|
|
_SS_WRITE(LOW);
|
|
WRITE(MOSI_PIN, HIGH); // Output 1s 1
|
|
uint8_t b = spiTransferRx(0xFF);
|
|
_SS_WRITE(HIGH);
|
|
return b;
|
|
}
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
if (nbyte) {
|
|
_SS_WRITE(LOW);
|
|
WRITE(MOSI_PIN, HIGH); // Output 1s 1
|
|
spiRxBlock(buf, nbyte);
|
|
_SS_WRITE(HIGH);
|
|
}
|
|
}
|
|
|
|
void spiSend(uint8_t b) {
|
|
_SS_WRITE(LOW);
|
|
(void)spiTransferTx(b);
|
|
_SS_WRITE(HIGH);
|
|
}
|
|
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
_SS_WRITE(LOW);
|
|
(void)spiTransferTx(token);
|
|
spiTxBlock(buf, 512);
|
|
_SS_WRITE(HIGH);
|
|
}
|
|
|
|
/**
|
|
* spiRate should be
|
|
* 0 : 8 - 10 MHz
|
|
* 1 : 4 - 5 MHz
|
|
* 2 : 2 - 2.5 MHz
|
|
* 3 : 1 - 1.25 MHz
|
|
* 4 : 500 - 625 kHz
|
|
* 5 : 250 - 312 kHz
|
|
* 6 : 125 - 156 kHz
|
|
*/
|
|
void spiInit(uint8_t spiRate) {
|
|
switch (spiRate) {
|
|
case 0:
|
|
spiTransferTx = (pfnSpiTransfer)spiTransferTx0;
|
|
spiTransferRx = (pfnSpiTransfer)spiTransferRx0;
|
|
spiTxBlock = (pfnSpiTxBlock)spiTxBlock0;
|
|
spiRxBlock = (pfnSpiRxBlock)spiRxBlock0;
|
|
break;
|
|
case 1:
|
|
spiTransferTx = (pfnSpiTransfer)spiTransfer1;
|
|
spiTransferRx = (pfnSpiTransfer)spiTransfer1;
|
|
spiTxBlock = (pfnSpiTxBlock)spiTxBlockX;
|
|
spiRxBlock = (pfnSpiRxBlock)spiRxBlockX;
|
|
break;
|
|
default:
|
|
spiDelayCyclesX4 = ((F_CPU) / 1000000) >> (6 - spiRate);
|
|
spiTransferTx = (pfnSpiTransfer)spiTransferX;
|
|
spiTransferRx = (pfnSpiTransfer)spiTransferX;
|
|
spiTxBlock = (pfnSpiTxBlock)spiTxBlockX;
|
|
spiRxBlock = (pfnSpiRxBlock)spiRxBlockX;
|
|
break;
|
|
}
|
|
|
|
_SS_WRITE(HIGH);
|
|
WRITE(MOSI_PIN, HIGH);
|
|
WRITE(SCK_PIN, LOW);
|
|
}
|
|
|
|
/** Begin SPI transaction, set clock, bit order, data mode */
|
|
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
|
// TODO: to be implemented
|
|
}
|
|
|
|
#pragma GCC reset_options
|
|
|
|
#else // !SOFTWARE_SPI
|
|
|
|
#define WHILE_TX(N) while ((SPI0->SPI_SR & SPI_SR_TDRE) == (N))
|
|
#define WHILE_RX(N) while ((SPI0->SPI_SR & SPI_SR_RDRF) == (N))
|
|
#define FLUSH_TX() do{ WHILE_RX(1) SPI0->SPI_RDR; }while(0)
|
|
|
|
#if MB(ALLIGATOR)
|
|
|
|
// slave selects controlled by SPI controller
|
|
// doesn't support changing SPI speeds for SD card
|
|
|
|
// --------------------------------------------------------------------------
|
|
// hardware SPI
|
|
// --------------------------------------------------------------------------
|
|
static bool spiInitialized = false;
|
|
|
|
void spiInit(uint8_t spiRate) {
|
|
if (spiInitialized) return;
|
|
|
|
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 };
|
|
if (spiRate > 6) spiRate = 1;
|
|
|
|
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
|
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
|
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
|
|
SPI_CSR_DLYBCT(1));
|
|
SPI_Enable(SPI0);
|
|
spiInitialized = true;
|
|
}
|
|
|
|
void spiBegin() {
|
|
if (spiInitialized) return;
|
|
|
|
// Configure SPI pins
|
|
PIO_Configure(
|
|
g_APinDescription[SCK_PIN].pPort,
|
|
g_APinDescription[SCK_PIN].ulPinType,
|
|
g_APinDescription[SCK_PIN].ulPin,
|
|
g_APinDescription[SCK_PIN].ulPinConfiguration);
|
|
PIO_Configure(
|
|
g_APinDescription[MOSI_PIN].pPort,
|
|
g_APinDescription[MOSI_PIN].ulPinType,
|
|
g_APinDescription[MOSI_PIN].ulPin,
|
|
g_APinDescription[MOSI_PIN].ulPinConfiguration);
|
|
PIO_Configure(
|
|
g_APinDescription[MISO_PIN].pPort,
|
|
g_APinDescription[MISO_PIN].ulPinType,
|
|
g_APinDescription[MISO_PIN].ulPin,
|
|
g_APinDescription[MISO_PIN].ulPinConfiguration);
|
|
|
|
// set master mode, peripheral select, fault detection
|
|
SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
|
|
SPI_Enable(SPI0);
|
|
|
|
SET_OUTPUT(DAC0_SYNC);
|
|
#if EXTRUDERS > 1
|
|
SET_OUTPUT(DAC1_SYNC);
|
|
WRITE(DAC1_SYNC, HIGH);
|
|
#endif
|
|
SET_OUTPUT(SPI_EEPROM1_CS);
|
|
SET_OUTPUT(SPI_EEPROM2_CS);
|
|
SET_OUTPUT(SPI_FLASH_CS);
|
|
WRITE(DAC0_SYNC, HIGH);
|
|
WRITE(SPI_EEPROM1_CS, HIGH);
|
|
WRITE(SPI_EEPROM2_CS, HIGH);
|
|
WRITE(SPI_FLASH_CS, HIGH);
|
|
WRITE(SS_PIN, HIGH);
|
|
|
|
OUT_WRITE(SDSS, LOW);
|
|
|
|
PIO_Configure(
|
|
g_APinDescription[SPI_PIN].pPort,
|
|
g_APinDescription[SPI_PIN].ulPinType,
|
|
g_APinDescription[SPI_PIN].ulPin,
|
|
g_APinDescription[SPI_PIN].ulPinConfiguration
|
|
);
|
|
|
|
spiInit(1);
|
|
}
|
|
|
|
// Read single byte from SPI
|
|
uint8_t spiRec() {
|
|
// write dummy byte with address and end transmission flag
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
|
|
WHILE_TX(0);
|
|
WHILE_RX(0);
|
|
|
|
//DELAY_US(1U);
|
|
return SPI0->SPI_RDR;
|
|
}
|
|
|
|
uint8_t spiRec(uint32_t chan) {
|
|
|
|
WHILE_TX(0);
|
|
FLUSH_RX();
|
|
|
|
// write dummy byte with address and end transmission flag
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
WHILE_RX(0);
|
|
|
|
return SPI0->SPI_RDR;
|
|
}
|
|
|
|
// Read from SPI into buffer
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
if (!nbyte) return;
|
|
--nbyte;
|
|
for (int i = 0; i < nbyte; i++) {
|
|
//WHILE_TX(0);
|
|
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
|
|
WHILE_RX(0);
|
|
buf[i] = SPI0->SPI_RDR;
|
|
//DELAY_US(1U);
|
|
}
|
|
buf[nbyte] = spiRec();
|
|
}
|
|
|
|
// Write single byte to SPI
|
|
void spiSend(const byte b) {
|
|
// write byte with address and end transmission flag
|
|
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
WHILE_TX(0);
|
|
WHILE_RX(0);
|
|
SPI0->SPI_RDR;
|
|
//DELAY_US(1U);
|
|
}
|
|
|
|
void spiSend(const uint8_t* buf, size_t nbyte) {
|
|
if (!nbyte) return;
|
|
--nbyte;
|
|
for (size_t i = 0; i < nbyte; i++) {
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
WHILE_TX(0);
|
|
WHILE_RX(0);
|
|
SPI0->SPI_RDR;
|
|
//DELAY_US(1U);
|
|
}
|
|
spiSend(buf[nbyte]);
|
|
}
|
|
|
|
void spiSend(uint32_t chan, byte b) {
|
|
WHILE_TX(0);
|
|
// write byte with address and end transmission flag
|
|
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
WHILE_RX(0);
|
|
FLUSH_RX();
|
|
}
|
|
|
|
void spiSend(uint32_t chan, const uint8_t* buf, size_t nbyte) {
|
|
if (!nbyte) return;
|
|
--nbyte;
|
|
for (size_t i = 0; i < nbyte; i++) {
|
|
WHILE_TX(0);
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
|
|
WHILE_RX(0);
|
|
FLUSH_RX();
|
|
}
|
|
spiSend(chan, buf[nbyte]);
|
|
}
|
|
|
|
// Write from buffer to SPI
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
|
|
WHILE_TX(0);
|
|
//WHILE_RX(0);
|
|
//SPI0->SPI_RDR;
|
|
for (int i = 0; i < 511; i++) {
|
|
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
WHILE_TX(0);
|
|
WHILE_RX(0);
|
|
SPI0->SPI_RDR;
|
|
//DELAY_US(1U);
|
|
}
|
|
spiSend(buf[511]);
|
|
}
|
|
|
|
/** Begin SPI transaction, set clock, bit order, data mode */
|
|
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
|
// TODO: to be implemented
|
|
}
|
|
|
|
#else // U8G compatible hardware SPI
|
|
|
|
#define SPI_MODE_0_DUE_HW 2 // DUE CPHA control bit is inverted
|
|
#define SPI_MODE_1_DUE_HW 3
|
|
#define SPI_MODE_2_DUE_HW 0
|
|
#define SPI_MODE_3_DUE_HW 1
|
|
|
|
/**
|
|
* The DUE SPI controller is set up so the upper word of the longword
|
|
* written to the transmit data register selects which SPI Chip Select
|
|
* Register is used. This allows different streams to have different SPI
|
|
* settings.
|
|
*
|
|
* In practice it's spooky. Some combinations hang the system, while others
|
|
* upset the peripheral device.
|
|
*
|
|
* SPI mode should be the same for all streams. The FYSETC_MINI_12864 gets
|
|
* upset if the clock phase changes after chip select goes active.
|
|
*
|
|
* SPI_CSR_CSAAT should be set for all streams. If not the WHILE_TX(0)
|
|
* macro returns immediately which can result in the SPI chip select going
|
|
* inactive before all the data has been sent.
|
|
*
|
|
* The TMC2130 library uses SPI0->SPI_CSR[3].
|
|
*
|
|
* The U8G hardware SPI uses SPI0->SPI_CSR[0]. The system hangs and/or the
|
|
* FYSETC_MINI_12864 gets upset if lower baud rates are used and the SD card
|
|
* is inserted or removed.
|
|
*
|
|
* The SD card uses SPI0->SPI_CSR[3]. Efforts were made to use [1] and [2]
|
|
* but they all resulted in hangs or garbage on the LCD.
|
|
*
|
|
* The SPI controlled chip selects are NOT enabled in the GPIO controller.
|
|
* The application must control the chip select.
|
|
*
|
|
* All of the above can be avoided by defining FORCE_SOFT_SPI to force the
|
|
* display to use software SPI.
|
|
*
|
|
*/
|
|
|
|
void spiInit(uint8_t spiRate=6) { // Default to slowest rate if not specified)
|
|
// Also sets U8G SPI rate to 4MHz and the SPI mode to 3
|
|
|
|
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 };
|
|
if (spiRate > 6) spiRate = 1;
|
|
|
|
// Enable PIOA and SPI0
|
|
REG_PMC_PCER0 = (1UL << ID_PIOA) | (1UL << ID_SPI0);
|
|
|
|
// Disable PIO on A26 and A27
|
|
REG_PIOA_PDR = 0x0C000000;
|
|
OUT_WRITE(SDSS, HIGH);
|
|
|
|
// Reset SPI0 (from sam lib)
|
|
SPI0->SPI_CR = SPI_CR_SPIDIS;
|
|
SPI0->SPI_CR = SPI_CR_SWRST;
|
|
SPI0->SPI_CR = SPI_CR_SWRST;
|
|
SPI0->SPI_CR = SPI_CR_SPIEN;
|
|
|
|
// TMC2103 compatible setup
|
|
// Master mode, no fault detection, PCS bits in data written to TDR select CSR register
|
|
SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS;
|
|
// SPI mode 3, 8 Bit data transfer, baud rate
|
|
SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDivider[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_3_DUE_HW; // use same CSR as TMC2130
|
|
SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDivider[1]) | SPI_CSR_CSAAT | SPI_MODE_3_DUE_HW; // U8G default to 4MHz
|
|
}
|
|
|
|
void spiBegin() { spiInit(); }
|
|
|
|
static uint8_t spiTransfer(uint8_t data) {
|
|
WHILE_TX(0);
|
|
SPI0->SPI_TDR = (uint32_t)data | 0x00070000UL; // Add TMC2130 PCS bits to every byte (use SPI0->SPI_CSR[3])
|
|
WHILE_TX(0);
|
|
WHILE_RX(0);
|
|
return SPI0->SPI_RDR;
|
|
}
|
|
|
|
uint8_t spiRec() { return (uint8_t)spiTransfer(0xFF); }
|
|
|
|
void spiRead(uint8_t* buf, uint16_t nbyte) {
|
|
for (int i = 0; i < nbyte; i++)
|
|
buf[i] = spiTransfer(0xFF);
|
|
}
|
|
|
|
void spiSend(uint8_t data) { spiTransfer(data); }
|
|
|
|
void spiSend(const uint8_t* buf, size_t nbyte) {
|
|
for (uint16_t i = 0; i < nbyte; i++)
|
|
spiTransfer(buf[i]);
|
|
}
|
|
|
|
void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
spiTransfer(token);
|
|
for (uint16_t i = 0; i < 512; i++)
|
|
spiTransfer(buf[i]);
|
|
}
|
|
|
|
#endif // !ALLIGATOR
|
|
#endif // !SOFTWARE_SPI
|
|
|
|
#endif // ARDUINO_ARCH_SAM
|